User manual PIONEER C-AX10 service manual

[. . . ] ORDER NO. DOLBY DIGITAL RRV2327 DIGITAL CONTROL AMPLIFIER C-AX10 THIS MANUAL IS APPLICABLE TO THE FOLLOWING MODEL(S) AND TYPE(S). Model Type C-AX10 KU/CA NY AC120V AC230V Power Requirement Remarks CONTENTS 1. 85 PIONEER ELECTRONIC CORPORATION 7. 1. 3 POWER ON SEQUENCE . . . . . . . . . . . . . . . . . . . . . . 95 7. 2 PARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7. 2. 1 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Keep distance with wire of CN1803 and FFC away and bind it. 11 Remove four connectors. Front side CN301 Pass a wire through a slit of the shield plate every one set (three sets). Note: It becomes an equal interval wires of each group. CN407 CN406 FRAD ASSY 1 Remove the DIGITAL I/O ASSY, DSP ASSY and Main Shield. Heat Sink Assy E FRAD ASSY CN405 4 5 6 4 12 2 ×2 2 ×2 Unhook Unhook Side Wall Power Cord F 3 CRAD ASSY Note: Slide the PC Board to rear slide (2 or 3 cm away) after removing screws, connectors, Heat Sink ASSY and Rear Panel. And PC Board can lift to upper side when matches a projection part of the Side Wall with a cut part of the PC Board. Remove the Shield Plate B where is in the bottom of CRAD ASSY. (Three screws) 93 C-AX10 Power Transformer (T301, T401) When replacing the Analog Transformer (T401) ( 1 to 5 ) 14 ×7 1 2 Remove the DIGITAL I/O ASSY, DSP ASSY and Main Shield. Remove three connectors. Front side CN405 B AC ASSY 15 Cut a Binder (ZCA-BK1). I FRAD ASSY Subchassis B2 CN406 CN407 19 17 ×4 16 4 6 5 ×4 T301 (Digital) 3 CN101 Remove CN102. T401 (Audio) UL Tube (KU/CA type only) 18 ×3 Unhook When replacing the Digital Transformer (T301) ( 7 to 19 ) Styling in installation (PS ASSY) T301 (Digital) 7 9 ×2 10 13 11 Remove two connectors. Front side Diode AC ASSY C PS ASSY B 8 C PS ASSY Bind two wires (Blue/Black). Unhook two PCB Supports. 12 Unhook three PCB Supports. Bind two wires (Green/Brown) (Be careful not to touch the Press down five wires except diode. ) blue and black wires to under side with a binder of PS ASSY. Caution: Keep Blue/Black wires, Green/Brown wires and other five wires away each other, and perform styling. 94 C-AX10 Front Panel Section 1 ×2 7. 1. 5 PCB LAYOUT G DSP ASSY Main Shield Power Trans. Rear Panel 2 ×3 PS ASSY A B SG ASSY AC ASSY 3 Unhook 4 79 F CRAD ASSY DIGITAL I/O ASSY D AUDIO A ASSY C Subchassis B2 Side Wall H Door 3 Unhook E O P Shield Plate I N K VOLUME ASSY J DISPLAY ASSY ENC B ASSY 5 Remove a binder. Subchassis T2 FRAD ASSY Side Frame A Side Support M INPUT SW ASSY Side Alum. L Side Wall L ENC A ASSY Under Base 6 Remove a wire. AU DIO S BA SY I Diagnosis Front Panel Assy Caution in installation Install the Door by the opened state when installing the Front Panel. (so that an installed earth wire is caught between the Door, and there is the case that the Door does not opend. ) Side Alum. R 95 C-AX10 7. 2 PARTS 7. 2. 1 IC · The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams. · List of IC TC74VHC257FT, TC74VHC244F, TC7WT74FU, TC74VHC4040FT, TC74VHC153FT, TC74VHC157F, TC74VHC163FT, DF1704E, BC4094BCFV, TC7W126FU, AT24C16N-10SI2. 5, M30622SFP, M38079SFP, AK5393VS TC74VHC257FT (DSP ASSY : IC1505) · Quad 2-Channel Multiplexer (3-state) · Block Diagram SELECT 1 1A 2 1B 3 2A 5 2B 6 3A 11 3B 10 4A 14 4B 13 OE 15 12 4Y 9 3Y 7 2Y 4 1Y · Truth Table INPUTS OE SELECT A H X X L L L L L H L H X L H X X : Don't Care Z : High Impedance B X X X L H OUTPUTS Z L H L H TC74VHC244F (DSP ASSY : IC1506) · Octal Bus Buffer · Pin Arrangement (Top view) 1G 1 1A1 2 2Y4 3 1A2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 GND 10 20 Vcc 19 2G 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 · Truth Table INPUTS G An L L L H H X OUTPUTS Yn L H Z X : Don't Care Z : High Impedance Yn : TC74VHC244F 96 C-AX10 TC7WT74FU (DSP ASSY : IC1605) · D-type Flip Flop with Present and Clear · Pin Arrangement (Top view) CK 1 D2 Q3 GND 4 C D S R 8 Vcc 7 PR 6 CLR 5Q · Truth Table INPUTS CLR PR D L H X H L X L L X H H L H H H H H X X : Don't Care CK X X X OUTPUTS FUNCTION Q Q L H CLEAR H L PRESET H H L H H L Qn Qn NO CHANGE TC74VHC4040FT (DSP ASSY : IC1606, IC1623) · 12-stage Ripple-carry Binary Counter · Block Diagram Q1 Q2 Q3 Q4 Q5 Q6 · Truth Table 9 7 6 5 3 2 CK CLR Output State X H All outputs "L" L Don't change L Go to the next state X : Don't Care D D CK Q R D CK Q R D CK Q R D CK Q R D CK Q R CK 10 CLR 11 CK Q R R Q CK D R Q CK D R Q CK D R Q CK D R Q CK D R Q CK D 1 Q12 15 Q11 14 Q10 12 Q9 13 Q8 4 Q7 97 C-AX10 TC74VHC153FT (DSP ASSY : IC1614) · Dual 4-channel Multiplexer · Block Diagram A 14 S0 S0 S1 B 2 S1 S2 S2 S3 S3 1C0 6 S0 1C1 5 S1 1C2 4 S2 1C3 3 S3 1G 2C0 2C1 2C2 2C3 1 10 11 12 13 7 1Y · Truth Table SELECT INPUTS B X L L L L H H H H A X L L H H L L H H C0 X L H X X X X X X DATA INPUTS C1 X X X L H X X X X C2 X X X X X L H X X C3 X X X X X X X L H STROBE OUTPUT G H L L L L L L L L Y L L H L H L H L H X : Don't Care 9 2Y Same as abobe block 2G 15 TC74VHC157F (DSP ASSY : IC1704, IC1804, IC1903, IC2003) · Quad 2-channel Multiplexer · Block Diagram 1A 2 4 1Y 1B 3 2A 5 7 2Y 2B 6 3A 11 9 3Y 3B 10 4A 14 12 4Y 4B 13 SELECT 1 ST 15 · Truth Table INPUTS ST SELECT A H X X L L L L L H L H X L H X X : Don't Care B X X X L H OUTPUT L L H L H 98 C-AX10 TC74VHC163FT (DSP ASSY : IC1620) · Synchronous Presettable 4-bit Counter · Block Diagram CLR 1 ENP 7 ENT 10 LOAD 9 L L 15 CARRY OUT A3 L L E CK Q D R Q · Truth Table D X L H X CK R H L L X Q L L H * Q H H L * E E X : Don't Care * : No Change 14 QA E B4 L L E CK Q D R Q 13 QB E C5 L L E CK Q D R Q 12 QC E D6 L L E CK Q D R Q 11 QD E CK 2 99 C-AX10 DF1704E (DSP ASSY : IC1902, IC2002) · Digital Filter · Block Diagram BCKIN 2 LRCIN 28 DIN 1 MD/CKO MC/LRIP ML/RESV MODE MUTE RST DEM 11 12 13 10 15 14 16 IIS IW0 IW1 34 5 OW0 OW1 20 19 26 BCKO 8X Oversampling Digital Filter with Fuction Controller Output I/F 25 WCKO 24 DOL 23 DOR Serial Input I/F Mode Control I/F SCK Crystal OSC Power Supply 17 18 27 SF0SF1 SRO 6 XTI 22 7 9 XTO CLKO VDD 8 Vss · Pin Function No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name DIN BCKIN IIS IW0 IW1 XTI XTO Vss CLKO MODE MD/CKO MC/LRIP ML/RESV RST MUTE DEM SF0 SF1 OW0 OW1 NC VDD DOR DOL WCKO BCKO SRO LRCIN I/O I I I I I I O - O I I I I I I I I I I I - - O O O O I I Serial audio data input Bit clock input for serial audio data Format selection of input audio data Word selection of input audio data Word selection of input audio data Connect an oscillator or external clock input Oscillator output Ground Buffer output of system clock Pin Function Mode control selection ( H: Software mode, L: hardware mode) Mode control, data / 1/2 divided clock selection Mode control, clock / LRCIN polarity selection Mode control, latch, clock / Not used Reset It becomes reset state during this pin is L. Mute control Deemphasis control Deemphasis Deemphasis Sampling rate selection Sampling rate selection Data word selection of output audio Data word selection of output audio Non connection Power supply +5V Serial audio data output of R ch Serial audio data output of L ch Word clock output for serial audio data output Bit clock output for serial audio data output Filter characteristic selection L/R clock input (fs) 100 C-AX10 BU4094BCFV (DSP ASSY : IC2101, IC2107, IC2108, IC2118) · Port Expander · Block Diagram DATA 2 CLOCK 3 8-STAGE SHIFT REGISTER 10 Q's 9 Qs · Truth Table OUTPUT SERIAL CLOCK STROBE DATA ENABLE OUTPUT ± ± ± ± L L H H H H X X L H H X X X X L H X PARALLEL OUTPUTS Q1 Qn Z Z Z Z No Chg. Qs STROBE 1 8-BIT LATCHES OUTPUT 15 ENABLE 4 Q1 3-STATE OUTPUTS X : Don't Care Z : High Impedance 14 Q8 PARALLEL OUTPUT · Pin Function No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mark STROBE_ SERIAL IN CLOCK Q1 Q2 Q3 Q4 VSS QS QS' Q8 Q7 Q6 Q5 OUTPUT ENABLE VDD STB Pin Name DATA CLOCK INPUT SEL 1 INPUT SEL 2 INPUT SEL 3 192KHz VSS QS QS' HI-BIT REC SEL 3 REC SEL 2 REC SEL 1 OE VDD I/O I I I O O - O O O O I - Strobe input (IC2102 pin 23) Pin Function Serial data input (IC2102 pin21) Serial clock input (IC2102 pin 22) INPUT selector 1 INPUT selector 2 INPUT selector 3 192kHz playback H: PDIF 192kHz signal VSS Connect to pin 2 (DATA) of IC2118 Not used Hi-bit playback H: Hi-bit playback REC selector 3 REC selector 2 REC selector 1 Chip enable input (IC2102 pin 28) VDD 101 C-AX10 TC7W126FU (DSP ASSY : IC2103, IC2114) · Dual Bus Buffer · Pin Arrangement (Top view) VCC 8 G2 7 Y1 6 A2 5 · Truth Table INPUTS G A L X H L H H OUTPUTS Y Z L H 1 G1 2 A1 3 Y2 4 GND X : Don't Care Z : High Impedance AT24C16N-10SI2. 5 (DSP ASSY : IC2106) · 2-wire Serial CMOS EEPROM · Block Diagram WP 7 SCL 6 SDA 5 START STOP LOGIC · Pin Function No. PUMP/TIMING 4 5 6 DATA RECOVERY 7 8 X DEC EEPROM A0 A1 A2 GND SDA SCL WP VCC Ground Serial data Serial clock input Write protect Power supply Address input Pin Function DEVICE ADDRESS COMPARATOR A2 3 A1 2 A0 1 R/W DATA WORD ADDR/COUNTER Y DEC SERIAL MUX VCC 8 GND 4 DIN DOUT/ACK LOGIC DOUT 102 C-AX10 M30622SFP (DSP ASSY : IC2102) · DSP Microcomputer · Pin Function No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Mark P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVSS P87/XCIN P86/XCOUT RESET_ XOUT VS S XIN VCC P85/NMI_ P84/INT2_ P83/INT1_ P82/INT0_ P81/TA4IN/U_ P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W_ P74/TA2OUT/W P73/CTS2_/RTS2_ /TA1IN/V_ P71/RXD2/SCL /TA0IN/TB5IN P67/TXD1 P66/RXD1 P65/CLK1 P64/CTS1_/RTS1_ /CTS0_/CLKS1 P63/TXD0 P62/RXD0 P61/CLK0 P60/CTS0_/RTS0_ P57/RDY_/CLKOUT P56/ALE P55/HOLD_ P54/HLDA_ P53/BCLK P52/RD_ P51/WRH_/BHE_ P50/WRL_/WR_ P47/CS3_ P46/CS2_ P45/CS1_ P44/CS0_ Pin Name DSP MOSI DSP SCK DF DEM DSP HREQ1 DATA out DATA in CLOCK BYTE CNVSS READY HCS2 RESET XOUT VSS XIN VCC NMI HCS1 ERFM ERFS S DATA S CLOCK EXSTB ADPARA FADPD SSDF HSSEL I/O O O O I O I I I I O O I O - I - I I I I O O O O O O O O O I O O O I O I O DSP communication clock output Pin Function DSP communication data output ( DSP) Deemphasis control of Surround and Center (IC1902 and IC2002) H: Deemphasis ON DSP communication ready ( center DSP) H: Communication busy Communcation data output of microcomputer ( main microcomputer) Communcation data input of microcomputer ( main microcomputer) Communcation clock input of microcomputer VOC (data length: 8 bit) Pull-up to VCC (external memory use mode) Microcomputer communication ready ( main microcomputer) H: Communication busy Microcomputer communication data request ( main microcomputer) L: Data request Reset input ( main microcomputer) Connect a 7. 7MHz ceramic resonator VSS Connect a 7. 7MHz ceramic resonator VCC (Not used) Pull-up to VCC Microcomputer communication data request ( main microcomputer) L: Data request Master DIR (IC1603) error H: unlock Slave DIR (IC1602) error H: unlock Serial data output Serial clock output Strobe output of expansion IC (IC2101 and IC2118) A/D (IC1105, IC2704 and IC2804) 3-parallel operation Front A/D (IC1105) power down L: Power down Legato DSP (IC1613) communication strobe L: Strobe ON CLK selection of center DSP (IC1501) H: PDIF 48 kHz/24 bit multi-channel Output enable of expansion IC (IC2101 and IC2118) H: Output enable Digital filter (IC1903 and IC2003) reset of surround and center PDIF cable detection H: Cable exist Legato DSP (IC1613) reset L: Reset Front DSP (IC1701, IC1702, IC1801 and IC1802) reset L: Reset TC74HC125AF (IC2112) control L: Version up P/C data request (version up) L: Communication ready Data output ( PDIF mutual certification of DV-AX10) / data output (version up) Data input ( PDIF mutual certification of DV-AX10) / data input (version up) (Not used) P/C data request (version up) L: Communication ready (Not used) Pull-up to VCC (Not used) (Not used) Pull-up to VCC (Not used) Output enable of Flash memory (IC2105) L: Output enable (Not used) Write enable of Flash memory (IC2105) L: Write enable (Not used) DIR (IC1603) CS/freq_ selection H: CS select CS control of Flash memory (IC2105) L: Chip enable L: Reset L: Strobe ON L: Analog 2ch input P72/CLK2/TA1OUT/V EXPOE X2CH P70/TXD2/SDA/TA0OUT PDIF DDRST FDRST VERUP CTS DATA out/ TXD (UART) DATA in/ RXD (UART) RTS RDY_ ALE HOLD_ HLDA_ BCLK OE# BHE_ WE# O I O I O O O O O CFSEL FLSHCS O O 103 C-AX10 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Mark P43/A19 P42/A18 P41/A17 P40/A16 P37/A15 P36/A14 P35/A13 P34/A12 P33/A11 P32/A10 P31/A9 VCC P30/A8(/-/D7) VSS P27/A7(/D7/D6) P26/A6(/D6/D5) P25/A5(/D5/D4) P24/A4(/D4/D3) P23/A3(/D3/D2) P22/A2(/D2/D2) P21/A1(/D1/D0) P20/A0(/D0/-) P17/D15/INT5_ P16/D14/INT4_ P15/D13/INT3_ P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3_ P106/AN6/KI2_ P105/AN5/KI1_ P104/AN4/KI0_ P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC Pin Name A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 VCC A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 DFRST DIR Ce/F2 LOCK DIR Cd/F1 DIR Cc/F0 DIR Cb/E2 DIR Ca/E1 DIR C0_/E0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CRADPD DSPMUTE CDRST DSP SSR1 DSP SSL1 DSP SSR2 DSP SSL2 AVSS DSP SSCT VREF AVCC DSP MISO I/O O (Not used) Pin Function O Communication address output of Flash memory (IC2105) - O - VCC Communication address output of Flash memory (IC2105) VSS O Communication address output of Flash memory (IC2105) O I I I I I I I Front digital filter (IC1703 and IC1803) reset L: Reset DIR (IC1603) CSe / freq report 2 PLL LOCK input H: PLL unlock DIR (IC1603) CSd / freq report 1 DIR (IC1603) CSc / freq report 0 DIR (IC1603) CSb / error condition 2 DIR (IC1603) CSa / error condition 1 DIR (IC1603) CS0_ / error condition 0 I/O Communication data input / output of Flash memory (IC2105) O O O O O O O - O - I Center and surround A/D (IC2704 and IC2804) power down L: Power down Digital filter (IC1703, IC1803, IC1902 and IC2002) mute Center DSP (IC1501) reset L: Reset Communication strobe of front DSP R1 (IC1801) Communication strobe of front DSP L1 (IC1701) Communication strobe of front DSP R2 (IC1802) Communication strobe of front DSP L2 (IC1702) VSS Communication strobe of center DSP (IC1501) VCC DSP communication data input ( DSP) L: Strobe ON L: Strobe ON L: Strobe ON L: Strobe ON L: Strobe ON H: Mute ON 100 P97/ADTRG_/SIN4 104 C-AX10 M38079SFP (DSP ASSY : IC2109) · System Microcomputer · Pin Function No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name P62/AN7 P61/AN6 P60/AN5 P77/AN4 P76/AN3 P75/AN2 P74/AN1 P73/Srdy2/AN0 P72/Sclk2 P71/Sout2 P70/Sin2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/Scmp2/INT2 P50/Tout P47/Srdy1 P46/Sclk1 P45/TxD P44/RxD P43/INT1 P42/INT0 CNVss RESET P41/Xcin P40/Xcout Xin Xout Vss P27/DB7 P26/DB6 P25/DB5 P24/DB4 P23/DB3 P22/DB2 P21/DB1 P20/DB0 I/O AD Main unit key input AD Not used AD I I O O O I O I I I I I I DSP MC bus (reset) General-purpose bus (clock) General-purpose bus (dataout) DSP MC bus (atain) DSP MC bus (cs) DSP MC bus (ready) DSP MC bus (interrupt) (request) SR signal input (interrupt) Digital filter lock detection (interrupt) DIR lock detection (interrupt) Encoder FL bus UART bus (lat/cts (I)) O I I FL bus UART bus (lock/dtr (O)) FL bus UART bus (dataout/txd) FL bus UART bus (datain/rxd) FL40V line control (dispoff) AC input (interrupt) Encoder Pin Function VSS connection (pull-down with 1k to 10k) Reset input O Output relay (F) Output relay (SW) Oscillator input Oscillator output - GND O Data bus of Flash ROM (db7 to db0) 105 C-AX10 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD9 P10/AD8 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P37/RD P36/WR P35/SYNC P34/Ckout/ P33/RESETout P32/ONW P31/RTP7 P30/RTP6 P87/RTP5 P86/RTP4 P85/RTP3 P84/RTP2 P83/RTP1 P82/RTP0 P81/DA4/AN12 P80/DA3/AN11 Vcc ADVref AVss P65/DAVref/AN10 P64/CMPref/AN9 P63/CMPin/AN8 CMPout CMPVcc I/O Pin Function O Address bus of Flash ROM (ad15 to ad2) O I O O O O I O O O O O O O O O O - Address bus of Flash ROM (ad1 to ad0) Flash ROM (read) Flash ROM (write) Flash ROM (sync) Flash ROM (clock) Flash ROM (reset) Flash ROM (cnw) Output relay (C) Output relay (SL/SR) FL bus (bk) Output enable for BU1092 XLOE DAC VOL (general-purpose bus) fsin DAC VOL (general-purpose bus) ldac LED driver (general-purpose bus) strobe I/O expander (general-purpose bus) strobe EEPROM backup EEPROM backup Power supply voltage 5. 0V Reference voltage Hi input for A/D converter Reference voltage Low input for A/D converter AD Position detect input 1 of Main volume AD Position detect input 0 of Main volume AD DNW SW input - Not used 106 C-AX10 AK5393VS (FRAD ASSY : IC1105 and CRAD ASSY : IC2704, IC2804) · Enhanced Dual-bit 108kHz 24-bit 2ch ADC · Block Diagram SMODE1 SMODE2 SCLK LRCK FSYNC 12 11 14 13 16 VREFL 1 GNDL 2 VCOML 3 AINL+ 4 AINL- 5 ZCAL 6 AINR+ 25 AINR- 24 VCOMR 26 VREFR 28 GNDR 27 23 VA Voltage Reference 22 21 AGND BGND Controller Calibration SRAM 7 VD 8 DGND Delta-Sigma Modulator Decimation Filter HPF 17 MCLK 18 DFS Delta-Sigma Modulator Decimation Filter HPF 19 HPFE Voltage Reference Serial Output Interface 15 SDATA 9 CAL 10 RST · Pin Function No. 1 2 3 4 5 6 7 8 9 Pin Name VREF GNDL VCOML AINL+ AINLZCAL VD DGND CAL I/O O - O I I I - - O Pin Function Reference voltage output pin for L ch, 3. 75V Connect an 10µF electrolytic capacitor and a 0. 1µF ceramic capacitor between this pin and GNDL. Reference ground pin for L ch, 0V Common voltage pin for L ch, 2. 75V Analog positive input pin for L ch Analog negative input pin for L ch Zero calibration Selects the reference signal for using the offset calibration. "L": VCOML, VCOMR , "H": Analog input pin (AIN ±, AINR ±) Power supply pin for digital section, 3. 3V Ground pin for digital section Calibration status pin Indicates that the during offset calibration at "H". Starts the calibration when RST pin becomes "H", and it beomes "L" after 8704LRCK cycled at DFS=L. Serial interface mode select pin MSB first, 2'S complement SMODE2 L L H H SMODE1 MODE LRCK L Slave mode: Front shorten H/ L H L H Master mode: Quasi I2S Slave mode: I2S Master mode: I2S H/ L L/H L/H 10 RST I 11 SMODE2 I 12 SMODE1 13 LRCK I/O Clock pin of L/R channel selection At SMODE1="H", it becomes "H" when SMODE2="L", and if becomes "L" when SMODE2="H" in the reset. 107 C-AX10 No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name SCLK SDATA FSYNC MCLK DFS HPFE TEST BGND AGND VA AINRAINR+ VCOMR GNDR VREFR I/O Pin Function Serial data clock pin Output data outputs 1-bit at falling edge of this pin. I/O Slave mode: clock more than 48fs is necessary Master mode: Output 128fs (DFS="L") and 64fs (DFS="H") clocks At reset= "L" O Serial data output pin MSB first, 2'S complement At reset= "L" Frame synchronous clock pin I/O Slave mode: SDATA output is enabled at "H" Master mode: 2fs clock output At reset= "L" I I I I - - - I I O - O Master clock input pin 256fs at DFS="L", 128fs at DFS="H" Double speed sampling mode select pin "L": Normal speed, "H": Double speed HPF enable pin "L": OFF, "H": ON Test pin Connect to DGND. PCB ground pin, 0V Ground pin for analog section, 0V Power supply pin for analog section, 5V Analog positive input pin for R ch Analog negative input pin for R ch Common voltage pin for R ch, 2. 5V Reference ground pin for R ch, 0V Reference voltage output pin for R ch, 3. 75V Connect an 10µF electrolytic capacitor and a 0. 1µF ceramic capacitor between this pin and GNDR. 108 C-AX10 7. 2. 2 Display AAV7065 (DISPLAY ASSY : V2201) · FL Display · Pin Assignment 1 72 · Grid Assignment a G1 b G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 c G1 d · Pin Connection Pin No. Connection 1 F1 2 F1 3 F1 4 - 58 NP 59 SI 60 61 VDD1 SO 62 LAT 63 BK 64 CLK 65 66 67 VSS VSS VDD2 68 NP 69 NP 70 F2 71 F2 72 F2 BD system pin out 109 C-AX10 7. 3 REMOTE CONTROL UNIT (CU-C005) NOTES: · Parts marked by "NSP" are generally unavailable because they are not in our Master Spare Parts List. · The mark found on some component parts indicates the importance of the safety factor of the part. Therefore, when replacing, be sure to use parts of identical designation. · Screws adjacent to mark on the product are used for disassembly. 7. 3. 1 Exploded View and Parts List 3 : Hook points (×14) 5 4 6 2 10 12 Diffusion Plate 1 9 8 11 7 Expladed View Parts List Mark No. 1 2 3 4 5 6 7 Description Filter Rubber Sheet Name Plate A Name Plate B Case A Slide Case Case B Part No. AZA7340 AZA7372 AZA7373 AZA7374 AZN7810 AZN7812 AZN7811 Mark No. 8 9 10 11 12 Description Terminal A (+) Terminal B (-) Contact Spring Battery Cover PCB for Remote Control Unit (AXD7198) Part No. AZB7141 AZB7142 AZB7143 AZN7813 AZW7256 110 1 2 3 4 C-AX10 7. 3. 2 Schematic Diagram A 49 41 33 R01 1(1/4W) D01 SID303C-01 Q01 2SC3265 R02 22 4 3 2 50 42 34 8 7 6 5 C02 0. 1µF 20 19 VDD CARR 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 51 43 35 12 11 10 9 52 44 36 16 15 14 13 45 37 20 19 18 17 46 38 24 23 22 21 47 39 28 27 26 25 48 40 32 31 30 29 KEY No. XX BATTERY 3V C01 10µF B IC01 M34280M1-352FP Vss 1 E2 2 E1 3 XIN XOUT E0 4 5 6 X1 G0 7 G1 8 G2 9 G3 10 3. 84MHz SWITCHES KEY No. [. . . ] 5 Hz ­ 44 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Sampling frequency: 96 kHz) Analogue input LINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hz ­ 20 kHz ±0. 3 dB Digital input jacks Coaxial 3-line: . . . . . . . . . . . . . . . . . . . . . . . . 0. 5 Vp-p(Input impedance: 75 ) Optical 3-line S/N ratio (Normal, 2-channel mode) Digital input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ]