User manual MATLAB EDA SIMULATOR LINK 3

[. . . ] EDA Simulator LinkTM 3 User's Guide How to Contact The MathWorks Web Newsgroup www. mathworks. com/contact_TS. html Technical Support www. mathworks. com comp. soft-sys. matlab suggest@mathworks. com bugs@mathworks. com doc@mathworks. com service@mathworks. com info@mathworks. com Product enhancement suggestions Bug reports Documentation error reports Order status, license renewals, passcodes Sales, pricing, and general information 508-647-7000 (Phone) 508-647-7001 (Fax) The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098 For contact information about worldwide offices, see the MathWorks Web site. EDA Simulator LinkTM User's Guide © COPYRIGHT 2003­2010 by The MathWorks, Inc. The software described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement. [. . . ] · Path specification can include ". " or "/" path delimiters, but cannot include a mixture. · The leaf module or signal must match the HDL language of the top-level module. The following examples show valid signal and module path specifications: top. port_or_sig /top/sub/port_or_sig top 4-19 4 Replacing an HDL Component with a Simulink Algorithm top/sub top. sub1. sub2 The following examples show invalid signal and module path specifications: · top. sub/port_or_sig Why this specification is invalid: You cannot use mixed delimiters. · :sub:port_or_sig : :sub Why this specification is invalid: When you use VHDL-specific delimiters you limit the interoperability with paths when moving between HDL simulators and between VHDL and Verilog. Path Specifications for Simulink Cosimulation Sessions with VHDL Top Level. · Path specification may include the top-level module name but it is not required. · Path specification can include ". " or "/" path delimiters, but cannot include a mixture. · The leaf module or signal must match the HDL language of the top-level module. The following examples show valid signal and module path specifications: top. port_or_sig /sub/port_or_sig top top/sub top. sub1. sub2 The following examples show invalid signal and module path specifications: · top. sub/port_or_sig Why this specification is invalid: You cannot use mixed delimiters. 4-20 Define the HDL Cosimulation Block Interface for Component Simulation · :sub:port_or_sig : :sub Why this specification is invalid: When you use VHDL-specific delimiters you limit the interoperability with paths when moving between HDL simulators and between VHDL and Verilog. Obtaining Signal Information Automatically from the HDL Simulator The Auto Fill button lets you begin an HDL simulator query and supply a path to a component or module in an HDL model under simulation in the HDL simulator. Usually, some change of the port information is required after the query completes. You must have the HDL simulator running with the HDL module loaded for Auto Fill to work. Note The example is based on a modified copy of the Manchester Receiver model, in which all signals were first deleted from the Ports and Clocks panes. 1 Open the block parameters dialog box for the HDL Cosimulation block. Click the Ports tab. The Ports pane opens (as an example, the Ports pane for the HDL Cosimulation block for use with ModelSim is shown in the illustrations below). 4-21 4 Replacing an HDL Component with a Simulink Algorithm Tip Delete all ports before performing Auto Fill to ensure that no unused signal remains in the Ports list at any time. 2 Click the Auto Fill button. The Auto Fill dialog box opens. 4-22 Define the HDL Cosimulation Block Interface for Component Simulation This modal dialog box requests an instance path to a component or module in your HDL model; here you enter an explicit HDL path into the edit field. The path you enter is not a file path and has nothing to do with the source files. 3 In this example, the Auto Fill feature obtains port data for a VHDL component called manchester. The HDL path is specified as /top/manchester (path specifications will vary depending on your HDL simulator; see "Specifying HDL Signal/Port and Module Paths for Cosimulation" on page 4-19). 4 Click OK to dismiss the dialog box and the query is transmitted. 5 After the HDL simulator returns the port data, the Auto Fill feature enters it into the Ports pane, as shown in the following figure. 4-23 4 Replacing an HDL Component with a Simulink Algorithm 6 Click Apply to commit the port additions. 7 Delete unused signals from Ports pane and add Clock signal. The preceding figure shows that the query entered clock, clock enable, and reset ports (labeled clk, enable, and reset respectively) into the ports list. Delete the enable and reset signals from the Ports pane, and, for Incisive and ModelSim users, add the clk signal in the Clocks pane. For Discovery users, enter the clk signal via the PreSimTcl property of the launchDiscovery function, as shown here: 'PreSimTcl', {'force manchester. clk 1 0, 0 5 -repeat 10'}, . . . Both methods results in the same signals being present in the HDL Cosimulation block, as shown in the next figures (examples shown for use with Incisive). 4-24 Define the HDL Cosimulation Block Interface for Component Simulation 4-25 4 Replacing an HDL Component with a Simulink Algorithm 8 Auto Fill returns default values for output ports: · Sample time: 1 · Data type: Inherit · Fraction length: Inherit You may need to change these values as required by your model. See also "Specifying the Signal Data Types" on page 3-35. 9 Before closing the HDL Cosimulation block parameters dialog box, click Apply to commit any edits you have made. 4-26 Define the HDL Cosimulation Block Interface for Component Simulation Observe that Auto Fill returned information about all inputs and outputs for the targeted component. In many cases, this will include signals that function in the HDL simulator but cannot be connected in the Simulink model. [. . . ] EDA Simulator Link software supports only a single rate DUT with one 8-bit input and one 8-bit output. Continue on to "Set Up FPGA Project Configuration Parameters GUI" on page 15-5. Set Up FPGA Project Configuration Parameters GUI In the MATLAB command window, type the following: > fpgamodelsetup(gcs) You can replace gcs with the name of any valid model. See fpgamodelsetup. Continue on to "Specify Simulink® HDL Coder Configuration Parameters" on page 15-6. 15-5 15 FPGA Hardware-in-the-Loop (HIL) Specify Simulink HDL Coder Configuration Parameters 1 From the model window, open the Configuration Parameters dialog box, and select the Simulink HDL Coder pane. 2 In the Simulink HDL Coder pane, select language and folder name. Continue on to "Specify FPGA HIL Configuration Parameters" on page 15-6. Specify FPGA HIL Configuration Parameters Open or navigate to the EDA Link FPGA Workflow pane, as shown in the following image. 1 Select Workflow: FPGA hardware-in-the-loop. 15-6 Workflow for Generating FPGA HIL 2 Select Output: FPGA bitstream and processor executable (EDA Simulator Link software selects the output type for you automatically). 3 Select Board: Avent Spartan-3A DSP DaVinci (EDA Simulator Link software selects this automatically for you, as it only supports this one board as of the current release). 4 Specify project name. [. . . ]