User manual HITACHI HD44780U

[. . . ] HD44780U (LCD-II) (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD44780U can display up to one 8-character line or two 8-character lines. [. . . ] CGRAM data is sent and received after this setting. 37 µs 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address. AC AC AC AC AC AC AC 37 µs Read busy 0 flag & address 1 BF Reads busy flag (BF) 0 µs indicating internal operation is being performed and reads address counter contents. 191 HD44780U Table 6 Instructions (cont) Code Execution Time (max) (when fcp or fOSC is 270 kHz) 37 µs tADD = 4 µs* 37 µs tADD = 4 µs* Execution time changes when frequency changes Example: When fcp or fOSC is 250 kHz, 37 µs × 270 = 40 µs 250 Instruction RS Write data to CG or DDRAM 1 R/ 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Write data Writes data into DDRAM or CGRAM. DDRAM: Display data RAM CGRAM: Character generator RAM ACG: CGRAM address ADD: DDRAM address (corresponds to cursor address) AC: Address counter used for both DD and CGRAM addresses Read data 1 from CG or DDRAM I/D I/D S S/C S/C R/L R/L DL N F BF BF 1 Read data = 1: = 0: = 1: = 1: = 0: = 1: = 0: = 1: = 1: = 1: = 1: = 0: Increment Decrement Accompanies display shift Display shift Cursor move Shift to the right Shift to the left 8 bits, DL = 0: 4 bits 2 lines, N = 0: 1 line 5 × 10 dots, F = 0: 5 × 8 dots Internally operating Instructions acceptable Note: -- indicates no effect. * After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address counter is updated. Busy signal (DB7 pin) Busy state Address counter (DB0 to DB6 pins) A t ADD A+1 Note: t ADD depends on the operation frequency t ADD = 1. 5/(f cp or f OSC ) seconds Figure 10 Address Counter Update 192 HD44780U Instruction Description Clear Display Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). Return Home Return home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. If S is 1, it will seem as if the cursor does not move but the display does. Also, writing into or reading out from CGRAM does not shift the display. Display On/Off Control D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but can be displayed instantly by setting D to 1. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 × 8 dot character font selection and in the 11th line for the 5 × 10 dot character font selection (Figure 13). B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 409. 6-ms intervals when f cp or fOSC is 250 kHz. (The blinking frequency changes according to fOSC or the reciprocal of fcp. For example, when fcp is 270 kHz, 409. 6 × 250/270 = 379. 2 ms. ) 193 HD44780U Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). [. . . ] Function set (Interface is 8 bits long. ) Wait for more than 4. 1 ms RS R/W DB7 DB6 DB5 DB4 000011 BF cannot be checked before this instruction. Function set (Interface is 8 bits long. ) Wait for more than 100 µs RS R/W DB7 DB6 DB5 DB4 000011 BF cannot be checked before this instruction. Function set (Interface is 8 bits long. ) RS R/W DB7 DB6 DB5 DB4 000010 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 1 0 0 0 0 0 F 0 0 0 0 0 1 10 ** 00 00 00 01 00 I/D S BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. [. . . ]